1. Field of the Invention
The present invention relates to a plasma display panel, and more particularly, to a plasma display panel having a reduced number of address electrodes to decrease power consumption while maintaining the same resolution.
2. Description of the Related Technology
In general, plasma display panels display images using a gas discharge phenomenon. They have excellent display capabilities including display capacity, luminance, contrast, afterimage, and viewing angle, and thus, they are prime candidates to replace CRTs. In plasma display panels, light is generated by excitation of a gas between electrodes with DC or AC voltage. The resulting UV radiation excites fluorescent substances located between the electrodes and the fluorescent substances emit light.
FIG. 1 is an exploded perspective view briefly showing a conventional plasma display panel. As shown in FIG. 1, a conventional plasma display panel 100′ includes front and rear glass substrates 110′ and 140′. The front glass substrate 110′ has a number of display electrodes 120′ (X display electrodes 121′ and Y display electrodes 122′) formed parallel on the lower surface thereof. The display electrodes 120′ are covered with a first dielectric layer 130′. The first dielectric layer 130′ has a protective layer 135′ formed on a surface thereof to protect the display electrodes 120′ and the first dielectric layer 130′ from discharge. The display electrodes 120′ have low-resistance bus electrodes 121a′ and 122a′ formed on a surface thereof to reduce voltage drop.
The rear glass substrate 140′ has a number of address electrodes 150′ formed parallel to one another on the upper surface thereof to supply address signals. The address electrodes 150′ have a second dielectric layer 160′ formed thereon, the second dielectric layer 160′ having a thickness sufficient to protect the address electrodes. The second dielectric layer 160′ has barriers 170′ formed on a surface thereof, and the barriers 170′ face one another so as to define discharge regions therebetween. The address electrodes 150′ are positioned in the regions between the respective barriers 170′ and are generally parallel to them. The address electrodes 150′ cross over the display electrodes 120′.
The barriers 170′ have a shape as shown in FIG. 1 such that they define discharge regions and minimize discharge interference in the vertical direction. In addition, fluorescent layers 180′ are formed on the second dielectric layer 160′ over the address electrodes 150′ and between the barriers 170′, and are configured to be excited by UV rays and emit a predetermined color of light. For example, the fluorescent layers 180′ may include red fluorescent layers 181′, green fluorescent layers 182′, and blue fluorescent layers 183′.
FIG. 2 is a diagrammatic view showing the relationship among the address electrodes, display electrodes, and barriers of the plasma display panel shown in FIG. 1. As shown in FIG. 2, the address electrodes 150′ are positioned between the barriers 170′ and are generally parallel to them. The display electrodes 120′ cross the address electrodes 150′ and the barriers 170′. Red, green, and blue fluorescent layers 181′, 182′, and 183′ are formed between the barriers 170′. FIG. 2 shows seven columns of address electrodes 150′, five rows of display electrodes 120′, and eighteen sub-pixels.
FIG. 3 is a diagrammatic view showing the relationship among the address electrodes, display electrodes, and pixels of the plasma display panel shown in FIG. 1.
As shown in FIG. 3, conventional address electrodes 150′ are configured in such a manner that each of three sub-pixels constituting a pixel 184′ has its own address electrode 150′ assigned to it. For example, a red fluorescent layer 181′, forming a red sub-pixel, has an address electrode 150′ assigned thereto, a green fluorescent layer 182′, forming a green sub-pixel, has another electrode 150′ assigned thereto, and a blue fluorescent layer 183′, forming a blue sub-pixel, has another electrode 150′ assigned thereto.
A conventional plasma display panel 100′, constructed as above, performs address discharge by applying a voltage higher than discharge initiation voltage between the X display electrodes 121′ and the address electrodes 150′. In addition, the electrical potential of the Y display electrodes 122′ is adjusted to temporarily generate discharge between the X and Y display electrodes 121′ and 122′ so that a charge builds up on each of the X and Y display electrode's surface. Such a charge build up on the X and Y display electrodes 121′ and 122′ due to address discharge is generally referred to as a wall charge. After the address discharge, a pulse voltage lower than the discharge initiation voltage is applied to the region between the X and Y display electrodes 121′ and 122′, in order to maintain discharge between the X and Y display electrodes 121′ and 122′, on which a wall charge has built up due to the address discharge. Such discharge between the X and Y display electrodes 121′ and 122′ is also referred to as a trickle discharge and occurs only to display electrodes 120′ on which a wall charge has built up due to address discharge. The trickle discharge emits UV rays, which excite fluorescent substances and generate a certain color of light.
As the resolution of plasma display panels increases, the number of address electrodes increases and the pitch, or spacing between any two adjacent electrodes among them decreases. A decrease in pitch among address electrodes increases capacitance of address electrodes and the amount of power consumed in driving the address electrodes increases, as the power is approximately calculated as CV2f, where C is the capacitance of the address electrodes, V is the voltage, and f is the frequency at which the voltage is changing. That is, in order to manufacture high-resolution plasma display panels, increase in power consumption of address electrodes has been an undesirable result. Since the discharge voltage applied to the address electrodes is substantially higher than in the case of the display electrodes, increase in capacitance of the address electrodes is directly linked with significant increase in overall power consumption of the plasma display panels.
In the case of full high definition (HD), for example, 1920 pixels (5760 sub-pixels) are necessary for horizontal resolution. In order to meet this requirement, the number of address electrodes is 5760, because each sub-pixel must have its own address electrode assigned thereto, as mentioned above. As a result, the distance between address electrodes decreases, the capacitance of the electrodes increases, the power consumption of plasma display panels increases severely, and cross-talk between the address electrodes increases. In addition, the instantaneous power (or peak power) which must be supplied by a circuit for example, tape carrier package(TCP), so as to apply a predetermined voltage to the address electrodes increases and heat generated by the circuit or panel rises drastically.